#ifndef __RK3128_RESET_H__
#define __RK3128_RESET_H__

#ifdef __cplusplus
extern "C" {
#endif

#define RK3128_RESET_CORE0_PO		(0)
#define RK3128_RESET_CORE1_PO		(1)
#define RK3128_RESET_CORE2_PO		(2)
#define RK3128_RESET_CORE3_PO		(3)
#define RK3128_RESET_CORE0			(4)
#define RK3128_RESET_CORE1			(5)
#define RK3128_RESET_CORE2			(6)
#define RK3128_RESET_CORE3			(7)
#define RK3128_RESET_CORE0_DBG		(8)
#define RK3128_RESET_CORE1_DBG		(9)
#define RK3128_RESET_CORE2_DBG		(10)
#define RK3128_RESET_CORE3_DBG		(11)
#define RK3128_RESET_TOPDBG			(12)
#define RK3128_RESET_ACLK_CORE		(13)
#define RK3128_RESET_STRC_SYS_A		(14)
#define RK3128_RESET_L2C			(15)

#define RK3128_RESET_CPUSYS_H		(18)
#define RK3128_RESET_AHB2APBSYS_H	(19)
#define RK3128_RESET_SPDIF			(20)
#define RK3128_RESET_INTMEM			(21)
#define RK3128_RESET_ROM			(22)
#define RK3128_RESET_PERI_NIU		(23)
#define RK3128_RESET_I2S_2CH		(24)
#define RK3128_RESET_I2S_8CH		(25)
#define RK3128_RESET_GPU_PVTM		(26)
#define RK3128_RESET_FUNC_PVTM		(27)
#define RK3128_RESET_CORE_PVTM		(29)
#define RK3128_RESET_EFUSE_P		(30)
#define RK3128_RESET_ACODEC_P		(31)

#define RK3128_RESET_GPIO0			(32)
#define RK3128_RESET_GPIO1			(33)
#define RK3128_RESET_GPIO2			(34)
#define RK3128_RESET_GPIO3			(35)
#define RK3128_RESET_MIPIPHY_P		(36)
#define RK3128_RESET_UART0			(39)
#define RK3128_RESET_UART1			(40)
#define RK3128_RESET_UART2			(41)
#define RK3128_RESET_I2C0			(43)
#define RK3128_RESET_I2C1			(44)
#define RK3128_RESET_I2C2			(45)
#define RK3128_RESET_I2C3			(46)
#define RK3128_RESET_SFC			(47)

#define RK3128_RESET_PWM			(48)
#define RK3128_RESET_DAP_PO			(50)
#define RK3128_RESET_DAP			(51)
#define RK3128_RESET_DAP_SYS		(52)
#define RK3128_RESET_CRYPTO			(53)
#define RK3128_RESET_GRF			(55)
#define RK3128_RESET_GMAC			(56)
#define RK3128_RESET_PERIPH_SYS_A	(57)
#define RK3128_RESET_PERIPH_SYS_H	(58)
#define RK3128_RESET_PERIPH_SYS_P	(59)
#define RK3128_RESET_SMART_CARD		(60)
#define RK3128_RESET_CPU_PERI		(61)
#define RK3128_RESET_EMEM_PERI		(62)
#define RK3128_RESET_USB_PERI		(63)

#define RK3128_RESET_DMA			(64)
#define RK3128_RESET_GPS			(67)
#define RK3128_RESET_NANDC			(68)
#define RK3128_RESET_USBOTG0		(69)
#define RK3128_RESET_OTGC0			(71)
#define RK3128_RESET_USBOTG1		(72)
#define RK3128_RESET_OTGC1			(74)
#define RK3128_RESET_DDRMSCH		(79)

#define RK3128_RESET_SDMMC			(81)
#define RK3128_RESET_SDIO			(82)
#define RK3128_RESET_EMMC			(83)
#define RK3128_RESET_SPI			(84)
#define RK3128_RESET_WDT			(86)
#define RK3128_RESET_SARADC			(87)
#define RK3128_RESET_DDRPHY			(88)
#define RK3128_RESET_DDRPHY_P		(89)
#define RK3128_RESET_DDRCTRL		(90)
#define RK3128_RESET_DDRCTRL_P		(91)
#define RK3128_RESET_TSP			(92)
#define RK3128_RESET_TSP_CLKIN		(93)
#define RK3128_RESET_HOST0_ECHI		(94)

#define RK3128_RESET_HDMI_P			(96)
#define RK3128_RESET_VIO_ARBI_H		(97)
#define RK3128_RESET_VIO0_A			(98)
#define RK3128_RESET_VIO_BUS_H		(99)
#define RK3128_RESET_VOP_A			(100)
#define RK3128_RESET_VOP_H			(101)
#define RK3128_RESET_VOP_D			(102)
#define RK3128_RESET_UTMI0			(103)
#define RK3128_RESET_UTMI1			(104)
#define RK3128_RESET_USBPOR			(105)
#define RK3128_RESET_IEP_A			(106)
#define RK3128_RESET_IEP_H			(107)
#define RK3128_RESET_RGA_A			(108)
#define RK3128_RESET_RGA_H			(109)
#define RK3128_RESET_CIF0			(110)
#define RK3128_RESET_PMU			(111)

#define RK3128_RESET_VCODEC_A		(112)
#define RK3128_RESET_VCODEC_H		(113)
#define RK3128_RESET_VIO1_A			(114)
#define RK3128_RESET_HEVC_CORE		(115)
#define RK3128_RESET_VCODEC_NIU_A	(116)
#define RK3128_RESET_PMU_NIU_P		(117)
#define RK3128_RESET_LCDC0_S		(119)
#define RK3128_RESET_GPU			(120)
#define RK3128_RESET_GPU_NIU_A		(122)
#define RK3128_RESET_EBC_A			(123)
#define RK3128_RESET_EBC_H			(124)

#define RK3128_RESET_CORE_DBG		(128)
#define RK3128_RESET_DBG_P			(129)
#define RK3128_RESET_TIMER0			(130)
#define RK3128_RESET_TIMER1			(131)
#define RK3128_RESET_TIMER2			(132)
#define RK3128_RESET_TIMER3			(133)
#define RK3128_RESET_TIMER4			(134)
#define RK3128_RESET_TIMER5			(135)
#define RK3128_RESET_VIO_H2P		(136)
#define RK3128_RESET_VIO_MIPI_DSI	(137)

#ifdef __cplusplus
}
#endif

#endif /* __RK3128_RESET_H__ */
